The invention relates to a receiving device for synchronous serial transmission data that are serially transmitted in synchronization with a clock signal.
FIG. 3 is a block diagram illustrating an example of a prior art data transmitting/receiving circuit for use in synchronous serial communication. In the figure, a reference numeral 100 generally represents a device on the transmitting end while a reference numeral 200 generally indicates a device on the receiving end.
The device on the transmitting end 100 includes a shift register 3, which temporarily holds a plurality of bit data prior to transmission, and a transmission data register 4 which transfers the transmission data in parallel to the shift register 3. This shift register 3 is connected in parallel with the transmission data register 4 in such a manner that corresponding bits of both registers are connected with each other. The transmission data register 4 is also connected to a bus line 5.
The device on the receiving end 200 includes a shift register 6 for receive data, a latch circuit 7 which latches the data after receiving it, a save register 8 for temporarily saving the data therein, an operational circuit 9, and a shift counter 10 for notifying the timing of the completion of data transfer.
A reference numeral 11 indicates a trigger input terminal, at which a clock signal CK for synchronous data transfer use is supplied to the shift register 3, the shift register 6, and the shift counter 10, respectively, as a synchronous clock signal. The shift-out terminal (Q) of the shift register 3 is connected to the shift-in terminal (D) of the shift register 6 in the device at the receiving end 200 via a serial transmission line 12.
Next, the operation of the data transmitting/receiving circuit as arranged above will be describe in the following.
As 8-bit transmission data A (A0.about.A7) are received on the bus line 5 of the device at the transmitting end 100, the data to be transmitted are temporarily stored in the transmission data register 4. Then, the data A are transferred in parallel to the shift register 3 and are held therein. These data as held in the shift register 3 are transmitted over the serial transmission line 12 on a bit-by-bit basis at every cycle of the clock signal CK received at the trigger input terminal 11, and then are transferred to the shift register 6 in the device at the receiving end 200. On one hand, while this operation is executed, the shift counter 10 counts the number of clock signals CK that have been received, in order to detect the time period that indicates the end of the data transfer. Detecting this time period, the shift counter 10 transmits a signal indicative of the end of the data transfer to the system over a transmission line 13.
At the time that the data transfer is completed, the data A (A0.about.A7), which had been transferred to the shift register 6, are latched in the latch circuit 7. After this, the first transferred data A are stored in the save register 8 as operand data.
Likewise, in the device at the receiving end 200, more data B (B0.about.B7) are received as operation data by the shift register 6 and are also latched by the latch circuit 7.
Finally, the operand data A (A0.about.A7) stored in the save register 8 in advance and the operation data B (B0.about.B7) later received and latched by the latch circuit 7, are provided to the operational circuit 9, which performs an intended operation . The result of this operation is provided to the system over a bus line 14.
However, in order to execute the operation with regard to the receive data A and B in the device at the receiving end 200 as arranged above, it is necessary to select the save register 8 and the operational circuit 9 such that they have bits that can correspond to all the bits of the shift register 6. Consequently, the device at the receiving end 200 must have a complex circuit arrangement. Furthermore, it is not possible to initiate the operation with regard to the operation data B (B0.about.B7) and the operand data A (A0.about.A7) until all the bits of the data B are completely transferred to the catch circuit 7. This means, therefore, that the receiving device as arranged above has a deficiency in that an unavoidable time lag exists, equivalent to the period of time from the start of data transfer to acquisition of the final operation result.